module time_base #(
    parameter integer SYS_CLK_FREQ = 10000000
) (
    input  sys_clk,
    input  rst_n,
    input  unit_sel_i,
    input  gate_ena_i,
    output tbase_pulse_1ms_o,
    output tbase_o
);

  wire tbase_1sec_s;
  wire tbase_100msec_s;
  wire tbase_1msec_s;

  sig_gate_gen #(
      .NCNTS(SYS_CLK_FREQ)
  ) gen_sig_gate_1sec (
      .sys_clk(sys_clk),
      .rst_n(rst_n),
      .start_i(gate_ena_i & (~unit_sel_i)),
      .sig_gate_o(tbase_1sec_s)
  );

  sig_gate_gen #(
      .NCNTS(SYS_CLK_FREQ / 10)
  ) gen_sig_gate_100ms (
      .sys_clk(sys_clk),
      .rst_n(rst_n),
      .start_i(gate_ena_i & unit_sel_i),
      .sig_gate_o(tbase_100msec_s)
  );

  clk_div #(
      .DIV_FACTOR(SYS_CLK_FREQ / 1000)
  ) gen_time_base_1msec (
      .rst_n  (rst_n),
      .clk_in (sys_clk),
      .clk_out(tbase_1msec_s)
  );

  reg tbase_1ms_d1;
  always @(posedge sys_clk, negedge rst_n) begin
    if (~rst_n) begin
      tbase_1ms_d1 <= 1'b0;
    end else begin
      tbase_1ms_d1 <= tbase_1msec_s;
    end
  end

  assign tbase_o = unit_sel_i ? tbase_100msec_s : tbase_1sec_s;
  assign tbase_pulse_1ms_o = tbase_1msec_s & (~tbase_1ms_d1);

endmodule
